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ADE7566/ADE7569
Table 15. Power Management Interrupt Fla g SFR (IPSMF, 0xF8)
Preliminary Technical Data
Bit No.
7
Address
0xFF
Mnemonic
FPSR
Default
0
Description
Power Supply Restored Interrupt Flag. Set when the V DD power supply has been restored.
This occurs when the source of V SW changes from V BAT to V DD .
6
5
4
3
0xFE
0xFD
0xFC
0xFB
FPSM
FSAG
RESERVED
FVADC
0
0
0
0
PSM Interrupt Flag. Set when an enabled PSM interrupt condition occurs.
Voltage SAG Interrupt Flag. Set when an ADE energy measurement SAG condition occurs.
This bit must be kept cleared for proper operation.
V DCIN Monitor Interrupt Flag. Set when V DCIN changes by VDCIN_DIFF or when V DCIN measurement is
ready.
2
1
0
0xFA
0xF9
0xF8
FBAT
FBSO
FVDCIN
0
0
0
V BAT Monitor Interrupt Flag. Set when V BAT falls below BATVTH or when V BAT measurement is ready.
Battery Switchover Interrupt Flag. Set when V SW switches from V DD to V BAT.
V DCIN Monitor Interrupt Flag. Set when V DCIN falls below 1.2 V.
Table 16. Battery Switchover Configuration SFR (BATPR, 0xF5)
Bit No.
7 to 2
1 to 0
Mnemonic
Reserved
BATPRG[1:0]
Default
00
00
Description
These bits must be kept to 0 for proper operation.
Control Bits for Battery Switchover.
BATPRG[1:0] Result
00 Battery switchover enabled on low V DD
01 Battery switchover enabled on low V DD and low V DCIN
1X Battery switchover disabled
Table 17. Peripheral Configuratio n SFR (PERIPH, 0xF4)
Bit No.
7
6
5
4
Mnemonic
RXFLAG
VSWSOURCE
VDD_OK
PLL_FLT
Default
0
1
1
0
Description
If set, indicates that an Rx edge event triggered wake-up from PSM2.
Indicates the power supply that is internally connected to V SW (0 V SW = V BAT , 1 V SW = V DD ).
If set, indicates that VDD power supply is ready for operation.
If set, indicates that a PLL fault occurred where the PLL lost lock. Set the PLLACK bit in the Start ADC
Measurement SFR (ADCGO, 0xD8) to acknowledge the fault and clear the PLL_FLT bit.
3
2
1 to 0
REF_BAT_EN
Reserved
RXPROG[1:0]
0
0
00
If set, internal voltage reference enabled in PSM2 mode. This bit should be set if LCD is on in PSM2 mode.
This bit should be kept to zero.
Controls the function of the P1.0/RxD pin.
RXPROG[1:0] Result
00 GPIO
01 RxD with wake-up disabled
11 RxD with wake-up enabled
Table 18. Power Management Interrupt Enable SFR (IPSME, 0xEC)
Bit No.
7
6
5
4
3
2
1
0
Interrupt Enable Bit
EPSR
RESERVED
ESAG
RESERVED
EVSW
EBAT
EBSO
EVDCIN
Default
0
0
0
0
0
0
0
0
Description
Enables a PSM interrupt when the power supply restored flag (FPSR) is set.
Reserved.
Enables a PSM interrupt when the voltage SAG flag (FSAG) is set.
This bit must be kept cleared for proper operation.
Enables a PSM interrupt when the V SW monitor flag (FVSW) is set.
Enables a PSM interrupt when the V BAT monitor flag (FBAT) is set.
Enables a PSM interrupt when the battery switchover flag (BSFO) is set.
Enables a PSM interrupt when the V DCIN monitor flag (FVDCIN) is set.
Rev. PrA | Page 24 of 136
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